As is well known, a final output stage of a generic electronic circuit basically includes a drive portion intended for powering a load. Thus, the output stage should be capable of draining or taking up current from the load, according to necessity and the type of application involved.
Countless configurations have been provided in the prior art for the output stage. FIG. 1 attached hereto shows schematically one of the most common such output stage configurations.
The output stage in FIG. 1 comprises a complementary pair of MOS transistors connected in series with each other, between a first voltage reference Vdd and a second voltage reference Vss, wherein the latter may either be a negative supply or a ground.
Complementary pairs of MOS transistors are mostly employed in output stages on account of the definite advantages that they afford as regards the control logics, however, the considerations made herein below would also apply to output stage configurations incorporating bipolar transistors or any other pairs of MOS transistors.
The first transistor M7 in the complementary pair is a pull-down transistor of either the NMOS or the DMOS type, and has its body terminal connected to its source terminal.
The second transistor M8 in the complementary pair is a pull-up transistor of the thin oxide PMOS type, and has its body terminal connected to its source terminal.
The transistors M8 and M7 are connected to each other through their respective drain terminals, which terminals coincide with an output node OUT. An electric load, not shown, is connected between this output node OUT and ground.
The electric load is driven alternately by the PMOS transistor M8 or the NMOS transistor M7, according to the different sourcing or of sinking operation modes.
Respective driver circuits have their respective outputs connected to the gate terminals of the transistors M8 and M7.
FIG. 1 shows, by way of example, a level shifter circuit for driving the transistors M7 and M8 of the final output stage thereby transferring an information from a low-voltage signal to a high-voltage signal. The circuit shown includes two NMOS drive transistors M1 and M2, two PMOS buffer transistors M4 and M3 effecting the voltage shift, and two additional PMOS transistors MS and M6 forming a bistable flip-flop for storing information about the state of the power PMOS M8. The gate terminal of the output PMOS M8 is connected to one, M3, of the two PMOS buffer transistors.
A shifter circuit of this kind also requires a reference voltage, to be obtained through a few zeners, for example, for biasing the gate terminals of the MOS buffer transistors M3 and M4.